Capture combination system

ABSTRACT

A capture combination system for use in an electronic organ provides rapid reprogramming of the entire combination memory while permitting manual selection of desired stop combinations at any time. Desired stop combinations are selected for each piston and set into the working memory of the system. These combinations, upon command, are transferred from the working memory to a storage or external memory. A full combination of stop settings may be stored on the external memory by transfer from the internal memory, and a number of such external memories corresponding to a number of different full combinations of stop settings thus may be prepared and, subsequently, selectively presented to the system as desired. The combination settings from the external memory are transferred upon command into the internal working memory for establishing the desired combination of stop settings therein. Transfer into or out of the external memory requires but a few seconds. Whenever desired, the working memory may be altered to modify one or more stop combinations, whether set manually, or entered therein from the external memory and, in the latter case, while retaining the combinations recorded in the external memory.

United States Patent 11 1 Molnar [45 May 15, 1973 [54] CAPTURE COMBINATION SYSTEM 3,366,93l 111968 Githens .340/1725 n 1 Inventor: mm Molnar. Twin. on 31223322; 141322 iiiv fijjfllIIIIW..n....IiIfiIi33iii512 [73] Assignee: North American Rockwell Corporaon, Anaheim Calif Primary ExammerPaul J. Henon Assistant Examiner-Jan E. Rhoads Flledi y 1972 Attorney-L. Lee Humphries [21] Appl. No.: 253,902

[57] ABSTRACT Related Applicant, A capture combination system for use in an electronic [62] Division of Ser. No 79,612, Oct. 9, 1970, Pat. No. org n provide rapid reprogramming of the entire 3,700,784 combination memory while permitting manual selection of desired stop combinations at any time. Desired [52] U.S. Cl. ,.340/l72,5, 84/101, 84/345 stop combinations are selected for each piston and set 34 370 into the working memory of the system. These com- 51 1111.131. ..G06f15/34 binations, upon command, are transferred from the 58 Field of Search ..340 172.5; 8411.01, Working memory to a storage or external y- A 34/102, 103 128, 345 full combination of stop settings may be stored on the external memory by transfer from the internal [56] References Cited memory, and a number of such external memories corresponding to a number of different full combina UNITED STATES PATENTS tions of stop settings thus may be prepared and, subsequently, selectively presented to the system as 3700784 10/1972 "84/345 desired. The combination settings from the external 323:2 et memory are transferred upon command into the inter- 365948B 5/1972 Detach: ,5 nal working memory for establishing the des1red com- 10/1971 Deutchm "Q bmation of stop settings there n. Transfer mto or out 3,610,799 0/1971 Watson v I I I I l "84/131 of the external memory requires but a few seconds. 3,651,481 3 1972 Evans et al 340 1725 whenever deslred, the workmg memory may be 3,648,255 3 1972 Beausoleil et a1 340 172 5 cred modify one Stop combinations- 3,6399|3 2/1972 Watson 340/172 5 whether set manually, or entered therein from the ex- 3 29 50 12 1 Clark et 1 340/172 5 ternal memory and, in the latter case, while retaining 3,629,842 12/1971 Taylor ..340/172.5 the Combinations recorded in the external y- 3.417,378 12/1963 Simonsen et a] 4 II7Z- 3,411,142 11/1968 Lee et al ..340/1725 7 Chums 64 Draw Figures CANEL READ plidtis' (emsn ts A 0 CENTRAL (Him Patented May 15, 1973 25 Sheets-Sheet 4.

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1. A data processing system responsive to input data for identification thereof and for controlling transfer of such data within said system, including transfer for entry into bit storage positions of an operating memory and for reading out of such data from said operating memory, for supply to utilization means, comprising: first means for presenting a plurality of input bits to said system, second means responsive to a plurality of control inputs, for selecting groups of said input data for transfer in said system, third means operable in a repeating cycle to respond to the input data presented by said first means for identification of groups thereof in accordance with time positions in said cycle, fourth means for serializing group of input data bits selected in accordance with the time position identification thereof in said cycle by said third means, an operating memory including a recirculating shift register having a predetermined number of data bit storage positions and driven in recirculation at a controlled cyclic rate and wherein the data bit storage positions thereof are assigned for storage of corresponding bits of input data, gating means responsive to the group selection by said second means in accordance with a control input for entering each said selected and serialized group of data bits into said shift register during the time interval of the recirculation cycle thereof when the storage bit positions assigned to the data bits of said group to be entered are recirculating in the external recirculation path of said shift register, said gating means further being responsive to the group selection by said second means for reading out from said recirculating shift register the stored input data bits of each group selected by said second means in accordance with said control inputs during the time interval of the recirculation cycle of said shift register when the thus identified, assigned storage bit positions thereof are recirculated in the external recirculation loop of such said shift register, and utilization means responsive to each said group of data bits thus derived from said shift register.
 2. A data processing system as recited in claim 1 wherein: said gating means is operable to enter into and read out from said shift register a single group of data bits as defined by said third means by selecting the corresponding time interval in the recirculation cycle of said recirculating shift register.
 3. A data processing system as recited in claim 1 and operable for transfer of storage data between said operating memory and said external memory for recording data, entered in said operating memory, in said external memory and for entering data recorded in said external memory into said operating memory, wherein there is further provided: means for defining a gating window of a time duration equal to the duration of recirculation of a single bit position of said shift register through said external recirculation loop of said shift register, and for producing said gating window in relation to the recirculation cycle of said shift register to withdraw a single data bit at a time from said shift register, in succeeding recirculation cycles thereof and successively for all data bit positions of said shift register, recording means for recording said data bits withdrawn from said shift register in the successive one bit duration gating windows in serial succession in said external memory, read means for reading said data bits from said external memory, and said gating window means further defines a one bit duration gating window in relation to the recirculation cycle of said shift register for entry of each such bit read from said external memory, in succession, into the corresponding storage bit position of said shift register then recirculating in the external circulation bit, in corrEsponding, successive recirculation cycles thereof.
 4. A data processing system as recited in claim 3 wherein there is further provided: means responsive to each of said one bit duration gating windows generated for withdrawing data bits from said recirculating shift register for generating a strobe pulse and for recording each such strobe pulse simultaneously in said external memory with the recording therein of a data bit.
 5. A data processing system as recited in claim 4 further comprising: means for reading the strobe pulses recorded in said external memory and responsive to each thereof for establishing an enabling interval for receipt of a corresponding data bit simultaneously read from said external memory, means responsive to said enabling interval for storing a corresponding data bit read from said external memory, and said gating window means being responsive to said data bit storing means for entering the data bit stored therein into said corresponding bit position of said shift register.
 6. A data processing system as recited in claim 4 wherein there is further provided: means for reading the strobe pulses and the corresponding data bits from said external memory, in succession for the plurality thereof, primary and secondary strobe pulses and data bit storage means responsive to said strobe pulses and corresponding data bits read from said external memory, said secondary means being disabled for receipt of strobe pulses and data bits until receipt of a strobe pulse and corresponding data bit by said primary means, said gating window means being responsive to said data bit storage means to enter the data bit stored therein in the corresponding bit position of said shift register, in each recirculation cycle thereof, said primary strobe and data bit storage means being cleared for receipt of a successive strobe pulse and corresponding data bits upon completion of the recirculation cycle by said gating window means, said secondary strobe pulse storage means being responsive to a successive strobe pulse received within said cycle and prior to reset of said primary means for disabling said primary means and storing said successive strobe pulse and corresponding data bit, and said primary means being enabled, when cleared, to receive the successive strobe pulse and data bit stored in said secondary means upon completion of said cycle, by said gating window means.
 7. A data processing system responsive to input data for identification thereof and entry into assigned storage locations of an operating memory and for transfer of such data between said operating memory and an external memory for recording the data in the external memory and for reading of data from the external memory for entry into said operating memory, comprising: first and second input means for presenting first and second sets of input data to said system, each bit of input data of said first set being associated with a group of input data of said second set, third means operable in a repeating cycle to scan said first input means to identify an input data bit presented thereat, recognition means for responding to the input data bit thus identified by said third means and including means responsive to the recognition of a data bit of said first means to identify the associated group of data bits of said second means, said third means being operable, in response to recognition of an input data bit from said first means, to scan said second means, an operating memory, gating means responsive to the identified data bit of said first means and the associated group of data bits of said second means, for identifying storage bit positions in said operating memory corresponding to those data bits of said second means, said gating means being selectively operable in response to an enter command and the identification of an input data bit presented by said first input means, to enter said data bits of said associated group derived from said second means into said assigned bit positions of said operating memory, and, in response to identification of a data bit presented by said first means, for reading out the data bits of the assigned bit positions of said operating memory and utilization means responsive to the data thus read out from said operating memory by said gating means. 